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Monday, July 18 • 8:00am - 5:00pm
Tutorial: Programming Intel's 2nd Generation Xeon Phi (Knights Landing)

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Intel's next generation Xeon Phi, Knights Landing (KNL), brings many changes from the first generation, Knights Corner (KNC). The new processor supports self-hosted nodes, connects cores via a mesh topology rather than a ring, and uses a new memory technology, MCDRAM. It is based on Intel’s x86 technology with wide vector units and hardware threads. Many of the lessons learned from using KNC do still apply, such as efficient multi-threading, optimized vectorization, and strided memory access.
This tutorial is designed for experienced programmers familiar with MPI and OpenMP. We’ll review the KNL architecture, and discuss the differences between KNC and KNL. We'll discuss the impact of the different MCDRAM memory configurations and the different modes of cluster configuration. Recommendations regarding MPI task layout when using KNL with the Intel OmniPath fabric will be provided.
As in past tutorials, we will focus on the use of reports and directives to improve vectorization and the implementation of proper memory access and alignment. We will also showcase new Intel VTune Amplifier XE capabilities that allow for in-depth memory access analysis and hybrid code profiling.

Monday July 18, 2016 8:00am - 5:00pm EDT
Merrick II